Computer Science 552:
Asynchronous VLSI Design (3.0 units)
Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
- Prerequisite: EE 477
- Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
- Crosslist: This course is offered by the EE department but may qualify for major credit in CSCI. To register, enroll in EE 552.
- Note: Register for lecture and discussion
|30702D||048||Lecture||6:40-9:20pm||Tuesday||31 of 47||Dan Gunnar Mika Nystroem||OHE100B|
|30703R||048||Discussion||12:00-12:50pm||Friday||31 of 47||OHE100D|
|30700D||034||Lecture||6:40-9:20pm||Tue, Thu||5 of 20||Dan Gunnar Mika Nystroem||DEN@Viterbi|
|30701R||034||Discussion||12:00-12:50pm||Friday||5 of 20||DEN@Viterbi|