The Fall 2020 semester will begin with fully remote instruction, with limited exceptions for clinical education. Faculty will contact students to provide information to login to classes. Read more.

Electrical and Computer Engineering 552:

Asynchronous VLSI Design (3.0 units)

Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
  • Prerequisite: EE 477
  • Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
  • Note: Register for lecture and discussion
SectionSessionTypeTimeDaysRegisteredInstructorLocationSyllabusInfo
30702D048Lecture6:40-9:20pmTuesday31 of 47Dan Gunnar Mika NystroemOHE100Bnotefeesession dates
30703R048Discussion12:00-12:50pmFriday31 of 47OHE100Dsession dates
30700D034Lecture6:40-9:20pmTue, Thu5 of 20Dan Gunnar Mika NystroemDEN@Viterbinotefeesession dates
30701R034Discussion12:00-12:50pmFriday5 of 20DEN@Viterbisession dates
Information accurate as of September 23, 2020 11:00 am.