Electrical and Computer Engineering 560L:
Digital System Design (4.0 units)
Hardware System Design and implementation, FPGAs, HDL design, timing, FIFOs, Cache, CAMs, SSRAMs, OoO/multi-threaded CPU design, cache coherency, clock-domain crossing, bus protocols. Prerequisite: EE 457.
- Prerequisite: EE 457
| Section | Session | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
|---|---|---|---|---|---|---|---|---|---|
| 30460D | 906 | Lecture | 1:30-4:20pm | Mon, Wed | 29 of 40 | Gandhi Puvvada | RTH105 |  | |
| 30462D | 906 | Lecture | 4:30-7:20pm | Tue, Thu | 28 of 40 | Gandhi Puvvada | RTH105 | | |
| 30463D | 911 | Lecture | 4:30-7:20pm | Tue, Thu | 11 of 18 | Gandhi Puvvada | DEN@Viterbi | | |
| 30464R | 906 | Lab | 4:30-5:50pm | Wednesday | 57 of 80 | GFS106 | | ||
| 4:30-5:50pm | Friday | GFS106 | |||||||
| 30465D | 911 | Lab | 4:30-5:50pm | Wednesday | 11 of 18 | DEN@Viterbi | | ||
| 4:30-5:50pm | Friday | DEN@Viterbi |