Electrical and Computer Engineering 560L:

Digital System Design (4.0 units)

Hardware System Design and implementation, FPGAs, HDL design, timing, FIFOs, Cache, CAMs, SSRAMs, OoO/multi-threaded CPU design, cache coherency, clock-domain crossing, bus protocols. Prerequisite: EE 457.
SectionSessionTypeTimeDaysRegisteredInstructorLocationSyllabusInfo
30460D906Lecture1:30-4:20pmMon, Wed31 of 40Gandhi PuvvadaRTH115session dates
30462D906Lecture4:30-7:20pmTue, Thu37 of 40Gandhi PuvvadaRTH105session dates
30463D911Lecture4:30-7:20pmTue, Thu7 of 10Gandhi PuvvadaDEN@Viterbisession dates
30464R906Lab4:30-5:50pmWednesday68 of 80GFS106session dates
4:30-5:50pm
Friday
GFS106
30465D911Lab4:30-5:50pmWednesday7 of 10DEN@Viterbisession dates
4:30-5:50pm
Friday
DEN@Viterbi
Information accurate as of January 23, 2023 1:44 pm.
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