Electrical and Computer Engineering 552:

Asynchronous VLSI Design (4.0 units)

Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous, locally synchronous design.
  • Prerequisite: EE 477
  • Restriction: Registration open to the following class level(s): Doctoral Student, Master Student
  • Note: Register for lecture and discussion
30702R048Lecture9:00-10:50amTue, Thu39 of 56Peter BeerelOHE132notesession dates
30703R048Discussion12:00-12:50pmFriday39 of 56OHE100Dsession dates
30700D034Lecture9:30-10:50amTue, Thu4 of 20Peter BeerelDEN@Viterbinotesession dates
30701R034Discussion12:00-12:50pmFriday4 of 20DEN@Viterbisession dates
Information accurate as of September 13, 2022 5:00 pm.
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