Computer Science 552:

Asynchronous VLSI Design (3.0 units)

Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
  • Prerequisite: EE 477
  • Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
  • Crosslist: This course is offered by the EE department but may qualify for major credit in CSCI. To register, enroll in EE 552.
  • Note: Register for lecture & discussion
SectionSessionTypeTimeDaysRegisteredInstructorLocationSyllabusInfo
30702D048Lecture9:30-10:50amTue, Thu23 of 47Peter BeerelOHE122 & ONLINEnotefeesession dates
30703R048Discussion12:00-12:50pmFriday23 of 47OHE120 & ONLINEsession dates
30700D034Lecture9:30-10:50amTue, Thu0 of 20Peter BeerelDEN@Viterbinotefeesession dates
30701R034Discussion12:00-12:50pmFriday0 of 20DEN@Viterbisession dates
Information accurate as of September 10, 2021 5:03 pm.
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