Electrical Engineering 552:
Asynchronous VLSI Design (3.0 units)
Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
- Prerequisite: EE 477
- Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
- Note: Register for lecture & discussion
Section | Session | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
---|---|---|---|---|---|---|---|---|---|
30702D | 048 | Lecture | 6:40-9:20pm | Tuesday | 13 of 45 | Dan Gunnar Mika Nystroem | RTH105 | ![]() ![]() ![]() | |
30703R | 048 | Discussion | 12:00-12:50pm | Friday | 13 of 56 | OHE100D | ![]() | ||
30700D | 034 | Lecture | 6:40-9:20pm | Tuesday | 1 of 20 | Dan Gunnar Mika Nystroem | DEN@Viterbi | ![]() ![]() ![]() | |
30701R | 034 | Discussion | 12:00-12:50pm | Friday | 1 of 20 | DEN@Viterbi | ![]() |