Electrical Engineering 552:

Asynchronous VLSI Design (3.0 units)

Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
  • Prerequisite: EE 477
  • Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
  • Note: Register for lecture and discussion
SectionSessionTypeTimeDaysRegisteredInstructorLocationSyllabusInfo
30702D048Lecture11:00-12:20pmTue, Thu36 of 56Peter BeerelOHE100Dnotefeesession dates
30703R048Discussion12:00-12:50pmFriday36 of 56OHE100Dsession dates
30700D034Lecture11:00-12:20pmTue, Thu1 of 20Peter BeerelDEN@Viterbinotefeesession dates
30701R034Discussion12:00-12:50pmFriday1 of 20DEN@Viterbisession dates
Information accurate as of September 13, 2017 11:08 am.