Electrical Engineering 560:

Digital System Design -- Tools and Techniques (3.0 units)

ASIC design, FPGAs, VHDL, verilog, test benches, simulation, synthesis, timing analysis, post-synthesis simulation, FIFOs, handshaking, memory interface, PCI bus protocol, CAD tools, design lab exercises. Recommended preparation: familiarity with CAD tools
SectionSessionTypeTimeDaysRegisteredInstructorLocationSyllabusInfo
30460D907Lecture2:00-3:50pmMon, Wed18 of 30Gandhi Puvvadafeesession dates
30464D907Discussion6:00-8:30pmWednesday18 of 48session dates
30462D907Lecture2:00-3:50pmTue, Thu29 of 48Gandhi Puvvadafeesession dates
30466D907Discussion6:00-8:30pmThursday29 of 48session dates
Information accurate as of 7/27/2015 2:19 PM.