Electrical Engineering 552:

Asynchronous VLSI Design (3.0 units)

Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
  • Prerequisite: EE 477
  • Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
  • Note: Register for lecture and discussion
SectionSessionTypeTimeDaysRegisteredInstructorLocationSyllabusInfo
30702D048Lecture11:00-12:20pmTue, Thu38 of 50Peter BeerelOHE100Dnotefeesession datesbook list
30703R048Discussion12:00-12:50pmFriday38 of 50OHE100Dsession dates
30700D034Lecture11:00-12:20pmTue, Thu3 of 20Peter BeerelDEN@Viterbinotefeesession datesbook list
30701R034Discussion12:00-12:50pmFriday3 of 20DEN@Viterbisession dates
30665D048Lecture5:00-7:50pmMonday
Canceled
feesession datesbook list
30449R048Discussion5:00-5:50pmThursday
Canceled
session dates
Information accurate as of 3/11/2015 2:55 PM.