Electrical Engineering 560:
Digital System Design -- Tools and Techniques (3.0 units)
ASIC design, FPGAs, VHDL, verilog, test benches, simulation, synthesis, timing analysis, post-synthesis simulation, FIFOs, handshaking, memory interface, PCI bus protocol, CAD tools, design lab exercises. Recommended preparation: familiarity with CAD tools
| Section | Session | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
|---|---|---|---|---|---|---|---|---|---|
| 30444D | 907 | Lecture | 2:00-3:30pm | Mon, Wed | 44 of 47 | Gandhi Puvvada | ZHS159 |    | |
| 30447D | 907 | Lecture | 2:00-3:50pm | Tue, Thu | 44 of 47 | Gandhi Puvvada | ZHS159 | | |
| 30485D | 907 | Lecture | 4:00-5:35pm | Mon, Wed | 44 of 47 | Gandhi Puvvada | ZHS159 | | |
| 30487D | 907 | Lecture | 4:00-5:35pm | Tue, Thu | 39 of 47 | Gandhi Puvvada | ZHS159 | | |
| 30439R | 907 | Discussion | 6:00-9:00pm | Tuesday | 46 of 47 | KAP160 | | ||
| 30445R | 907 | Discussion | 6:00-9:00pm | Monday | 37 of 47 | KAP160 | | ||
| 30486R | 907 | Discussion | 6:00-9:00pm | Wednesday | 46 of 47 | KAP160 | | ||
| 30488R | 907 | Discussion | 6:00-9:00pm | Thursday | 42 of 47 | KAP160 | |