Tuesday 06/26/2012: 10:00 AM - 11:30 AM
IBM T. J. Watson Research Center
A Cross-layer Framework for Monitoring and Mitigating Wearout
Speaker: Bardia Zandian, MHI Ph.D. Scholar
Efforts to continue with CMOS scaling while improving performance and controlling power consumption have resulted in accelerated processor wearout. In the first part of this talk, I’ll present WearMon, a cross-layer framework for monitoring circuit runtime wearout. WearMon uses adaptive critical path testing to provide a real-time measure of a processor's wearout-induced timing margin degradation. I will then present a design time refinement that significantly improves the efficiency and implementation feasibility of WearMon. The refinement uses path timing information and application-driven path utilization profile to isolate and target only a few critical paths for wearout monitoring even in the presence of a steep critical path timing wall.
In the second part of my talk, I’ll present a framework to increase the lifespan of a chip using wearout-aware scheduling polices. This framework uses real-time wearout information from a network of wearout sensors on the chip to adjust the utilization of different structures on the chip. Wear-leveling prevents early failure of a chip due to excessive wearout of a few vulnerable structures.
Location: IBM T.J. Watson Research Center - Yorktown Heights, NY