University of Southern California

Ming Hsieh Institute (MHI)

Search Events

  • Quantum Information Seminar - Domenico D'Alessandro

    Friday 06/08/2012: 2:00 PM - 3:00 PM
    University Park Campus SSL 150
  • Presentation at IBM T. J. Watson Research Center - Bardia Zandian, MHI PhD Scholar

    Tuesday 06/26/2012: 10:00 AM - 11:30 AM
    IBM T. J. Watson Research Center Yorktown Heights NY

    Title:

    A Cross-layer Framework for Monitoring and Mitigating Wearout

    Speaker:  Bardia Zandian, MHI Ph.D. Scholar


    Abstract:
    Efforts to continue with CMOS scaling while improving performance and controlling power consumption have resulted in accelerated processor wearout. In the first part of this talk, I’ll present WearMon, a cross-layer framework for monitoring circuit runtime wearout. WearMon uses adaptive critical path testing to provide a real-time measure of a processor's wearout-induced timing margin degradation. I will then present a design time refinement that significantly improves the efficiency and implementation feasibility of WearMon. The refinement uses path timing information and application-driven path utilization profile to isolate and target only a few critical paths for wearout monitoring even in the presence of a steep critical path timing wall.

    In the second part of my talk, I’ll present a framework to increase the lifespan of a chip using wearout-aware scheduling polices. This framework uses real-time wearout information from a network of wearout sensors on the chip to adjust the utilization of different structures on the chip. Wear-leveling prevents early failure of a chip due to excessive wearout of a few vulnerable structures. 

    Location:   IBM T.J. Watson Research Center - Yorktown Heights, NY

  • Presentation at 42nd Annual IEEE/IFIP International Conference (DSN 2012) - Bardia Zandian, MHI PhD Scholar

    Thursday 06/28/2012: 10:30 AM - 12:00 PM
    Boston Park Plaza Hotel Boston MA

    Title:

    Software-based Infield Wearout Monitoring for Synchronous Digital Chips

    Abstract:

    A software-based framework to measure wearout of synchronous digital chips as they are being utilized by end users is presented. First, a group of inputs to the chip, selected to sensitize the most critical paths of the circuit, are fed in while the chip is operating at nominal operation frequency and the correct expected outputs for these inputs are stored. Then clock frequency of the chip is increased and the same tests are repeated. Failure of a test to produce correct expected output at the elevated frequency will be used as an indication of the amount of wearout the circuit.

    Speaker: Bardia Zandia, MHI Ph.D. Scholar 

    Location: The 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)