Electrical Engineering 560:
Digital System Design -- Tools and Techniques (3.0 units)
ASIC design, FPGAs, VHDL, verilog, test benches, simulation, synthesis, timing analysis, post-synthesis simulation, FIFOs, handshaking, memory interface, PCI bus protocol, CAD tools, design lab exercises. Recommended preparation: familiarity with CAD tools
| Session | Section | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
|---|---|---|---|---|---|---|---|---|---|
| 907 | 30444D | Lecture | 2:00-3:35pm | Mon, Wed | 36 of 40 | Gandhi Puvvada | SLH102 |   | |
| 907 | 30485D | Lecture | 4:00-5:35pm | Mon, Wed | 37 of 40 | Gandhi Puvvada | SLH102 | | |
| 907 | 30445D | Discussion | 6:00-9:00pm | Monday | 37 of 44 | RTH105 | | ||
| 907 | 30486D | Discussion | 6:00-9:00pm | Wednesday | 34 of 44 | RTH105 | |
Information accurate as of 2/13/2009 3:08 PM.